1. Field of the Invention
The present invention relates to a power semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a power semiconductor device for use in an inverter and a method of manufacturing the same.
2. Description of the Background Art
In recent years, motors have gone inverter-driven, for example, in the field of air conditioning in terms of energy saving, and an increasing number of power semiconductor devices for inverters have been produced.
There is an increasing need for such power semiconductor devices not only to reduce power dissipation but also to reduce size and costs in terms of space saving.
A background art power semiconductor device is described below with reference to FIGS. 38 through 43. FIG. 38 is a circuit diagram of a three-phase inverter IV.
As illustrated in FIG. 38, the three-phase inverter IV comprises three inverters IV1 to IV3. The inverter IV1 includes IGBTs (insulated gate bipolar transistors, which are in some cases referred to simply as transistors hereinafter) Q1L and Q1U connected in series between a power supply line P providing a power supply voltage VDD and a power supply line N connected to a ground potential, and free wheeling diodes D1L and D1U connected in inverse-parallel with the transistors Q1L and Q1U, respectively. A connection node between the transistors Q1L and Q1U is connected to a first end of a load LU.
The inverter IV2 is similar in construction to the inverter IV1. Specifically, the inverter IV2 includes transistors Q2L and Q2U connected in series between the power supply lines P and N, and free wheeling diodes D2L and D2U connected in inverseparallel with the transistors Q2L and Q2U, respectively. A connection node between the transistors Q2L and Q2U is connected to a first end of a load LW.
Likewise, the inverter IV3 includes transistors Q3L and Q3U connected in series between the power supply lines P and N, and free wheeling diodes D3L and D3U connected in inverse-parallel with the transistors Q3L and Q3U, respectively. A connection node between the transistors Q3L and Q3U is connected to a first end of a load LV. The loads LU, LV and LW have respective second ends connected together.
In part of the inverter IV1 shown in FIG. 38 which is comprised of the transistor Q1L and the diode D1L, the reference characters E, C and G designate the emitter, collector and gate terminals of the transistor Q1L, respectively. The diode D1L has an anode terminal connected to the emitter terminal E and a cathode terminal connected to the collector terminal C.
A cross-sectional structure of the transistor Q1L and the diode D1L is described with reference to FIG. 39. In the description below, it is assumed that the transistor Q1L is of an n-channel type and the diode D1L is a diode having a p-type anode formed on an n-type semiconductor substrate.
As illustrated in FIG. 39, the transistor Q1L includes a p-type base region 8 formed in an upper main surface of an n-type silicon substrate 1T, and a plurality of trench-type gate electrodes 11 arranged in parallel and each extending through the p-type base region 8 in the direction of the depth thereof. A plurality of p-type semiconductor regions 12 containing a p-type impurity of a relatively high concentration are selectively formed in the surface of the p-type base region 8 in such a manner that each lies between adjacent two of the gate electrodes 11. The p-type semiconductor regions 12 are provided for the purpose of making a satisfactory electric connection between the p-type base region 8 and emitter electrodes 19.
A plurality of n-type emitter regions 9 containing an n-type impurity of a relatively high concentration are formed on the opposite sides of the respective p-type semiconductor regions 12. The n-type emitter regions 9 are designed to contact respective gate insulation films (not shown) formed on the surface of the gate electrodes 11. The silicon substrate 1T serves herein as an n-type base layer of the IGBT.
The emitter electrodes 19 formed partially on the surface of the n-type emitter regions 9 are electrically connected to the emitter terminal E. The gate electrodes 11 are electrically connected to the gate terminal G. A plurality of parallel-connected IGBT structures constitute the transistor Q1L A region in which the p-type base region 8, the n-type emitter regions 9 and the gate electrodes 11 are formed is referred to hereinafter as a cell region 2TC.
A plurality of p-type semiconductor regions 28 at a floating potential are arranged concentrically so as to surround the cell region 2TC, to define an electric field relieving ring region 2TG. The structure of the cell region 2TC and the electric field relieving ring region 2TG is generically referred to as an emitter-side structure 2.
An n-type buffer layer 3a is formed on a lower main surface of the silicon substrate 1T. A p-type collector layer 4 is formed on the surface of the n-type buffer layer 3a, and a collector electrode 5a of metal is formed on the surface of the p-type collector layer 4.
FIG. 40 is a plan view of the transistor Q1L as viewed from above the emitter electrode. As illustrated in FIG. 40, the transistor Q1L is formed on a rectangular board, and is configured such that the rectangular electric field relieving ring region 2TG surrounds the rectangular cell region 2TC. An n-type semiconductor region 27 at a floating potential is formed to surround the electric field relieving ring region 2TG.
In the cell region 2TC, a plurality of gate lines GL are arranged in parallel, and are connected at their respective ends to a gate ring region GR defining the outer periphery of the cell region 2TC. All of the gate lines GL are at a common potential. A gate pad GP is partially provided for electric connection between the gate lines GL and the exterior.
The spaces between the gate lines GL are covered with the emitter electrodes 19, and an upper emitter electrode 190 for making electric connections between the emitter electrodes 19 covers the emitter electrodes 19. For purposes of illustration, the upper emitter electrode 190 is shown with parts broken away in FIG. 40.
The cross-section of the transistor Q1L shown in FIG. 39 is a cross-section taken along the line A--A of FIG. 40. The gate electrodes 11 shown in FIG. 39 are only some of a plurality of gate electrodes 11 arranged longitudinally of the gate lines GL and each extending perpendicularly to the length of the gate lines GL.
Referring again to FIG. 39, the diode D1L includes a p-type anode layer 29 formed in an upper main surface of an n-type silicon substrate 1D. A anode electrode not shown is formed on the surface of the anode layer 29, and is electrically connected to the emitter terminal E. A region in which the anode layer 29 and the anode electrode are formed is referred to as an anode region 2DA.
A plurality of p-type semiconductor regions 28 at a floating potential are arranged concentrically so as to surround the anode region 2DA, to define an electric field relieving ring region 2DG. The structure of the anode region 2DA and the electric field relieving ring region 2DG is generically referred to as an anode-side structure 2D.
An n-type buffer layer 3b is formed on a lower main surface of the silicon substrate 1D. An n-type semiconductor layer 6 containing an n-type impurity of a relatively high concentration is formed on the surface of the n-type buffer layer 3b, and a cathode electrode 5b of metal is formed on the surface of the n-type semiconductor layer 6. The cathode electrode 5b is electrically connected to the collector terminal C.
The n-type semiconductor layer 6 is a layer for providing an ohmic contact between the cathode electrode 5b and the n-type buffer layer 3b. The silicon substrate 1D is a layer corresponding to an "i" (intrinsic) layer of the pin diode.
FIG. 41 is a plan view of the diode D1L as viewed form above the anode electrode. As illustrated in FIG. 41, the diode D1L is formed on a rectangular board, and is configured such that the rectangular electric field relieving ring region 2DG surrounds the rectangular anode region 2DA. An n-type semiconductor region 27 at a floating potential is formed to surround the electric field relieving ring region 2DG.
The cross-section of the diode D1L shown in FIG. 39 is a cross-section taken along the line B--B of FIG. 41. The anode layer 29 shown in FIG. 39 is only part of the actual anode layer 29.
As stated above, an arrangement having two devices arranged in parallel, i.e., the IGBT and the free wheeling diode which are formed separately has been employed to provide the three-phase inverter IV. Such an arrangement is disadvantageous in the increased module area of the three-phase inverter.
To overcome the disadvantage, an arrangement has been developed in which a free wheeling diode is incorporated in an IGBT. The arrangement in which the free wheeling diode is incorporated in the IGBT is discussed below with reference to FIGS. 42 and 43.
FIG. 42 is a cross-sectional view of an IGBT 90 with a free wheeling diode incorporated therein. The IGBT 90 is similar in basic construction to the transistor Q1L described with reference to FIG. 39. Like reference characters are used to designate parts identical with those of FIG. 39, and a repetition of description will be avoided. An emitter-side structure 2 shown in FIG. 42 corresponds to the emitter-side structure 2 of FIG. 39, and both of them are substantially identical. The silicon substrate is shown in FIG. 39 is referred to hereinafter as an n-type base layer 1.
The IGBT 90 includes an n-type buffer layer 3; a p-type collector layer 4 selectively formed in a main surface of the n-type buffer layer 3 in corresponding relation to a region in which the p-type base region 8 is formed (i.e., the cell region 2TC shown in FIG. 39); an n-type cathode region 6 selectively formed so as to surround the p-type collector layer 4 in spaced apart relation to the p-type collector layer 4; and a collector electrode 5 of metal in contact with the n-type buffer layer 3, the p-type collector layer 4 and the n-type cathode region 6.
Two current paths (a) and (b) shown in FIG. 42 are described in detail with reference to FIG. 43.
FIG. 43 shows part of the plurality of IGBT structures which includes two gate electrodes 11. The gate insulation films 10 which are not shown in FIGS. 39 and 42 are shown in FIG. 43. The gate insulation films 10 are formed to surround the respective gate electrodes 11. Application of a predetermined potential to the gate electrodes 11 inverts the conductivity type of part of the p-type base region 8 adjacent to the gate insulation films 10 to form a channel between the n-type emitter regions 9 and the n-type base layer 1.
As illustrated in FIG. 43, the current path (a) includes the emitter electrode 19, the p-type semiconductor region 12, the p-type base region 8, the n-type base layer 1, the n-type buffer layer 3, the n-type cathode region 6, and the collector electrode 5. The current path (b) includes the collector electrode 5, the p-type collector layer 4, the n-type buffer layer 3, the n-type base layer 1, the p-type base region 8, the n-type emitter region 9, and the emitter electrode 19.
Thus, two IGBT structures are arranged in parallel along the current path (b), and a free-wheeling diode parasitic upon the IGBT is present along the current path (a). Although the structure for constituting the current path (a) and the structure for constituting the current path (b) are shown separately for purposes of illustration in FIG. 43, both of the structures are common for the most part.
The operation of the IGBT 90 is described below. When a negative voltage is applied to the collector terminal C, a pn junction comprised of the p-type collector layer 4 and the n-type buffer layer 3 does not allow current to flow along the current path (b), but current flows along the current path (a) to bring about a diode operation.
However since the collector electrode 5, the n-type buffer layer 3, the n-type base layer 1 and the emitter-side structure 2 are common to the current paths (a) and (b), when a positive voltage is applied to the collector terminal C, a current path (c) extending from the collector electrode 5 through the n-type cathode region 6 to the n-type buffer layer 3 is formed to increase the potential of the n-type buffer layer 3, making it difficult for a voltage Vx between the n-type buffer layer 3 and the p-type collector layer 4 to reach a voltage high enough to cause conductivity modulation. As a result, the IGBT so constructed does not act as an IGBT but acts as a MOS field effect transistor (MOS transistor).
To avoid such an erroneous action, it is necessary to decrease the area of the n-type cathode region 6 and part of the n-type buffer layer 3 which constitute the free wheeling diode and to increase the area of the p-type collector layer 4, thereby decreasing a current ix flowing through a resistor Rx.
However, the decrease in the area of the n-type cathode region 6 (and the part of the n-type buffer layer 3) increases a forward voltage Vf of the free wheeling diode during the operation of the constituents of the current path (a), i.e., the free wheeling diode, and causes an on-state current and a recovery current of the free wheeling diode to concentrate on the n-type cathode region 6 (and the part of the n-type buffer layer 3) to increase a current density, which might result in device breakdown.
The background art inverter has been constructed such that two separately formed devices, i.e. the IGBT and the free wheeling diode, are arranged in parallel or such that the free wheeling diode is incorporated in the IGBT. The former has the disadvantage of increasing the module area of the inverter. The latter is disadvantageous in that turning on the IGBT requires as small the area of the n-type cathode region 6 as possible for suppression of the increase in potential of the n-type buffer layer 3, resulting in a strong likelihood of the device breakdown due to current concentration during the operation of the free wheeling diode.